Many integrated circuits (“ICs”) are made up of millions of interconnected devices, such as transistors, resistors, capacitors, and diodes, on a single chip of semiconductor substrate. Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks, also known as Block RAM, (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
An FPGA typically includes configurable logic blocks (CLBs), programmable input/output blocks (IOBs), and other types of logic blocks, such as memories, microprocessors, digital signal processors (DSPs), and the like. The CLBs, IOBs, and other logic blocks are interconnected by a programmable interconnect structure. The CLBs, IOBs, logic blocks, and interconnect structure are typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells that define how the CLBs, IOBs, logic blocks, and interconnect structure are configured. An FPGA may also include various dedicated logic circuits, such as digital clock managers (DCMs), input/output (I/O) transceivers, boundary scan logic, and the like.
Configurable logic devices, such as CPLDs and FPGAs, are configured to a particular application(s) by loading configuration data from a memory, typically at power-up. The configuration data may be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The configuration data is read from a ROM, PROM, EPROM, optical disk, magnetic disk, or other suitable source (“configuration source”). In CPLDs, configuration data is typically stored on-chip in non-volatile memory. Various techniques have been developed for ensuring that the configuration data accurately configures the device. One approach is to use a cyclical redundancy check (“CRC”), which is done after the entire set of configuration data has been loaded, to check whether the data was correctly transferred. In a CRC technique, a signature at the end of the configuration sequence is READ and compared with an expected signature. This approach is suitable for highly reliable configuration sources and READ techniques, or for relatively short sets of configuration data; however, in large configurable logic devices, such as an FPGA, it is undesirable to load a large set of configuration data, only to find that the configuration is not valid. The CRC can be used to validate data coming from configuration memory. It can also be used in a process where the SRAM in the PLD is readback and validated.
Another technique used to validate configuration data involves using a multiple input signature register (“MISR”). Using a MISR technique, a signature at the end of the configuration sequence is read and compared with an expected signature. The signature is accumulated as data is read from the configuration source, so the signature provides a valid indication of the integrity of the configuration data. However, the MISR technique uses the entire configuration data set, which can take a considerable time to download for some FPGAs. The MISR can be used to validate data coming from configuration memory. It can also be used in a process where the SRAM in the PLD is readback and validated.
A technique called “T-bits” has been developed for checking configuration integrity of CPLDs. A T-bit technique uses two bits of read-check data for each data address. The two bits are checked to see if they read the correct values as configuration proceeds. T-bit data is mixed into the bitstream, which is acceptable for relatively simple configuration data sets, but for larger configuration data sets, it can consume an unreasonable proportion of the memory.
Techniques for reliably and efficiently configuring FPGAs and other programmable logic devices are desired.